Efficient modeling of preemption in a virtual prototype

Abstract

A virtual prototype combines a hardware model with hardware/software cosimulation to support the development and debugging of embedded software before a hardware prototype is available. Existing techniques for hardware/software cosimulation execute the software either on an instruction set simulator for accuracy or on the simulator host processor for increased performance. On the host processor timing is either completely ignored or approximated using timing annotations in the code. Although preemption (interrupts) can strongly influence the timing, it is rarely modeled to avoid a performance degrading that would make the virtual prototype unusable, especially for real time signal processing software simulations which is already time consuming as such. We propose a technique to accurately model preemption and its effect on software timing in a simulation based on host code execution. Our technique has been implemented in the TIPSY C++ library for executable system modeling, pseudo C-code for this implementation with several optimizations is included in this paper. With this implementation, a preemptive scheduler model can be easily be created or taken from a library and inserted in a system model without changing the original code to observe the effect of preemption on the system behavior.