Design of a CMOS Highly Linear Channel-Select Filter and Programmable Gain Amplifier for a WPAN Zero-IF Receiver

Abstract

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier (PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance (Gm) cell. The PGA has a voltage gain varying from 0 to 65 dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85 dB THD and a 78 dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18 mum 1P6M n-well CMOS process. They consume 3.2 mW from a 1.8 V power supply and occupy an area of 0.19 mm 2