Readability challenges in deeply scaled STT-MRAM

W. Kang, Yuanqing Cheng, Youguang Zhang, D. Ravelosona, Weisheng Zhao
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引用次数: 10

Abstract

Spin transfer torque magnetic random access memory (STT-MRAM) is currently under intensive investigation for one of the possible alternatives to extend the Moore's Law beyond the CMOS technology scaling limit. Its advantageous features, such as nonvolatility, high speed, low power and excellent scalability etc, attract worldwide R&D attention. However as technology scales (e.g., below 40 nm), the process variations introduce big read reliability challenges for STT-MRAM due to the reduced sensing margin (SM) and the increased read disturbance (RD). Therefore the readability, rather than writability, will become an ultimate bottleneck of STT-MRAM at technology nodes below 40 nm. In this paper, we firstly analyze the technology scaling trends on the STT-MRAM read performance; and then we present a RD detection circuit for the case where read current is lower than the write current (e.g., >30 nm); finally we propose a reconfigurable cell design based on the differential sensing scheme to improve the SM and to reduce the RD simultaneously, for the case where read current approaches the write current (e.g., <;30 nm).
深度缩放STT-MRAM的可读性挑战
自旋转移转矩磁随机存取存储器(STT-MRAM)是目前正在深入研究的一种可能的替代方案,以扩展摩尔定律超越CMOS技术的缩放限制。其非易失性、高速度、低功耗和优良的可扩展性等优点,吸引了世界各国的研发关注。然而,随着技术规模的扩大(例如,低于40纳米),由于传感裕度(SM)的减少和读取干扰(RD)的增加,工艺变化给STT-MRAM带来了巨大的读取可靠性挑战。因此,在40 nm以下的技术节点上,可读性而非可写性将成为STT-MRAM的最终瓶颈。本文首先分析了STT-MRAM读写性能的技术尺度变化趋势;然后,我们提出了一种读电流低于写电流(例如,>30 nm)的RD检测电路;最后,我们提出了一种基于差分传感方案的可重构电池设计,以提高SM并同时降低RD,适用于读电流接近写电流(例如< 30 nm)的情况。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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