A network processor architecture for flexible QoS control in very high-speed line interfaces

2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552) Pub Date : 2001-05-29 DOI:10.1109/HPSR.2001.923669

H. Shimonishi, T. Murase

引用次数: 16

Abstract

We developed a network processor architecture that can be used for very high-speed line interfaces of carrier-class backbone routers and switches. Because advanced queuing and packet scheduling mechanisms are implemented as a software routine without the need for any special hardware components, the architecture provides a flexible QoS control mechanism and enables effective header handling.

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在非常高速的线路接口中实现灵活QoS控制的网络处理器体系结构

我们开发了一种网络处理器架构，可用于电信级骨干路由器和交换机的高速线路接口。由于高级队列和包调度机制作为软件例程实现，而不需要任何特殊的硬件组件，因此该体系结构提供了灵活的QoS控制机制，并支持有效的报头处理。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)

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