Power Integrity Analysis for High Current Digital Core & DDR Power and PDN Noise Impact on the LpDDR4 Timing Analysis for ADAS Automotive Application

Abstract

Power Distribution Networks (PDNs) in high-speed applications are very important for proper functioning of the IC's. In this paper, the impact of VRM, PCB, IC package and DIE parasitic on PDN is analyzed and how to optimize the PCB in order to achieve the target impedance for high current requirements. The holistic signal integrity approach of considering the coupling of DDR power noise on the parallel interface, affecting the timing and eye quality is studied.