Performance Evaluation of Vertically Stacked Nanosheet InGaAs/InAlAs/InP Double Quantum Well FinFET on Si Substrate

Abstract

We study the performance of vertically stacked InGaAs/InAlAs/InP Double Quantum Well (DQW) Fin Field Effect Transistor (FinFET) on Si substrate using threedimensional Technology Computer-Aided Design (TCAD) simulation. In0.53Ga0.47As and In0.52Al0.48As are used as the quantum well channel and the barrier material, respectively. Both materials are lattice matched to the InP buffer layer material on Si substrate. The device is simulated with gate lengths (LG) of 15 nm and gate stack (Al2O3/HfO2) of 1nm/2nm (EOT~0.75nm). The simulation results reveal that by using double channel quantum well (super lattice structure) can enhance the saturation current up to 24% compared to Single Quantum Well (SQW) device. The maximum capacitance of the DQW also outperforms the SQW FinFET approximately 34%. The higher capacitance indicates the higher carrier density. The electron density of DQW prefers to localize in the InGaAs layer as the quantum well channel, thus allow greater control over the electron behavior. The device characteristics indicate that the DQW FinFET on Si substrate can be alternated to enhance the device performance for prospective high performance logic device applications.