FPL Demo: Hot Reconfiguration - Partial Reconfiguration without Bounds

Abstract

Traditionally, partial reconfiguration of FPGAs involves replacing defined regions of the design, entirely replacing the logic and losing the state within that region. However, configuration frame reloads typically being glitch free means that wires and logic can safely be added and removed at runtime, without losing state - potentially even without stopping the clock! This could even be extended into an “edit and continue” mode where register positions and unchanged logic is preserved, and only changed logic cones are replaced, to enable small design changes to be made to a live system with only a brief pause and no loss of state.