A new CMOS analog multiplier with improved input linearity

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings Pub Date : 1995-11-06 DOI:10.1109/TENCON.1995.496355

Xiangluan Jia, W. Huang, Shi-Cai Qin

引用次数: 3

Abstract

A new CMOS four-quadrant analog multiplier is presented. By means of an unique nonlinear compensation technique, the linear input range of the multiplier is extended significantly. The simulation results show that, when V/sub y/=/spl plusmn/3V, the nonlinear error is less than 0.94% over the /spl plusmn/3V input range of V/sub x/ and when V/sub x/=/spl plusmn/3V, the nonlinear error is less than 0.25% over the /spl plusmn/3V input range of V/sub y/, with a power supply of /spl plusmn/5V.

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一种改进输入线性度的新型CMOS模拟乘法器

提出了一种新的CMOS四象限模拟乘法器。通过一种独特的非线性补偿技术，使乘法器的线性输入范围得到了显著的扩展。仿真结果表明，当V/sub y/=/spl plusmn/3V时，在V/sub x/的/spl plusmn/3V输入范围内的非线性误差小于0.94%;当V/sub x/=/spl plusmn/3V输入范围内的非线性误差小于0.25%，电源为/spl plusmn/5V。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings

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