Design of FLASH switch with flexible controllability

Abstract

We propose a new ATM switch with flexible buffering architecture and priority scheduling for providing a variety of QoS classes in this paper. In addition, this paper is concerned with the problem of supporting multiple QoS classes according to cell loss sensitivity and cell delay sensitivity. Loss-sensitive cells are given a higher priority to access a buffer with large free space to ensure a smaller cell loss probability, while delay-sensitive cells are assigned to a smaller buffer with high access priority to the output link to meet the shorter delay requirements. We also describe the implementation of a flexible ATM switch, FLASH (flexible ATM switch with high performance). FLASH also allows for multi-rate switching, supporting arbitrary-sized logical bit pipes with varying bandwidths. A notable characteristic is that FLASH provides multi-channel switching and guarantees cell sequence integrity without additional resequencing logic in the output port processors.