Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment

2009 10th Latin American Test Workshop Pub Date : 2009-03-02 DOI:10.1109/LATW.2009.4813817

J. Semião, J. Freijedo, M. Moraes, M. Mallmann, C. Antunes, J. Benfica, F. Vargas, Marcelino B. Santos, I. Teixeira, J. Rodríguez-Andina, João Paulo Teixeira, D. Lupi, E. Gatti, L. Garcia, F. Hernandez

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引用次数: 7

Abstract

As IC technology scales down, signal integrity issues such as power supply noise and clock skews are becoming one of the major concerns of gigahertz system-on-chip (SoC) design. Considering that one of the most important mechanisms to degrade signal integrity is electromagnetic interference (EMI), this paper analyzes the effectiveness of a clock duty-cycle (CDC) modulation technique to enhance SoC signal integrity with respect to power/ground voltage transients induced by EMI. The technique is based on a clock stretching logic (CSL) block, which monitors abnormal power grid activity and increases CDC accordingly. Practical experiments based on the implementation of a 32-bit soft-core pipeline processor in an FPGA IC were performed and illustrate the circuit robustness enhancement to power line fluctuations while maintaining at-speed clock rate. These experiments were conducted according to the IEC 62.132-2. Normative for measurement of radiated electromagnetic immunity (TEM-cell method).

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电磁干扰环境下单片系统时钟信号调制效率的测量

随着集成电路技术的缩小，信号完整性问题，如电源噪声和时钟偏差，正成为千兆赫系统级芯片(SoC)设计的主要问题之一。考虑到降低信号完整性的最重要机制之一是电磁干扰(EMI)，本文分析了时钟占空比(CDC)调制技术在电磁干扰引起的电源/地电压瞬变中提高SoC信号完整性的有效性。该技术基于时钟扩展逻辑(CSL)块，可监测电网异常活动并相应提高CDC。通过在FPGA上实现32位软核流水线处理器的实际实验，说明了在保持高速时钟速率的情况下，电路对电力线波动的鲁棒性增强。这些实验是根据IEC 62.132-2进行的。辐射电磁抗扰度测量规范(TEM-cell法)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2009 10th Latin American Test Workshop

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