Verification of decimal floating-point fused-multiply-add operation

Abstract

Decimal floating-point fused-multiply-add (FMA) software or hardware designs require a verification process to prove that the design is in compliance with the IEEE Standard for Floating-Point Arithmetic (IEEE Std 754–2008). Our work represents the first verification technique to verify the decimal FMA designs using simulation based coverage models. The paper describes in details the coverage models needed in the verification of the decimal FMA, the FMA engine used to solve the coverage models, and the results of using that technique in the verification of SilMinds FMA hardware design, DecNumber FMA software design, and Intel-Decimal Floating point Library FMA software design. The Technique has proven its efficiency in discovering bugs in FMA software and hardware designs.