Ying-Yao Lin, Wen-Kai Li, Pi-An Wu, Chih-Lung Chen, Yibin Hsieh, Eric Lu, Edris Rostami, Bryan Huang, Bart Wu, J. Ko, K. Fong, Y. Huang, Chun-Yi Wu, Chia-Hsin Wu, A. Jerng
{"title":"A 2×2 MIMO 802.11 b/g/n WLAN SOC in 55nm CMOS for AP/Router application","authors":"Ying-Yao Lin, Wen-Kai Li, Pi-An Wu, Chih-Lung Chen, Yibin Hsieh, Eric Lu, Edris Rostami, Bryan Huang, Bart Wu, J. Ko, K. Fong, Y. Huang, Chun-Yi Wu, Chia-Hsin Wu, A. Jerng","doi":"10.1109/ASSCC.2013.6691016","DOIUrl":null,"url":null,"abstract":"A single-chip 2×2 MIMO 802.11 b/g/n compliant WLAN AP/Router system-on-a chip(AP/Router SOC) that integrates all RF, analog, digital PHY, MAC, CPU and 5-port Ethernet functions as well as all necessary peripheral blocks has been integrated in 55nm CMOS. To reduce rBOM and PCB design complexity, two high power CMOS PAs, LNAs, and T/R switches are integrated for the MIMO transceiver. The radio transmits 22.4 dBm CCK mask compliant power and delivers 19dBm with EVM= -30dB at HT20 and 18dBm with EVM= -30dB at HT40. CCK RX sensitivity at the shared antenna port is -99dBm at 1Mbps rate, while CCK RX sensitivity is -100dBm at the auxiliary LNA path.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691016","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A single-chip 2×2 MIMO 802.11 b/g/n compliant WLAN AP/Router system-on-a chip(AP/Router SOC) that integrates all RF, analog, digital PHY, MAC, CPU and 5-port Ethernet functions as well as all necessary peripheral blocks has been integrated in 55nm CMOS. To reduce rBOM and PCB design complexity, two high power CMOS PAs, LNAs, and T/R switches are integrated for the MIMO transceiver. The radio transmits 22.4 dBm CCK mask compliant power and delivers 19dBm with EVM= -30dB at HT20 and 18dBm with EVM= -30dB at HT40. CCK RX sensitivity at the shared antenna port is -99dBm at 1Mbps rate, while CCK RX sensitivity is -100dBm at the auxiliary LNA path.