A high speed KDL-RAM file system for parallel computers

Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications Pub Date : 1990-03-07 DOI:10.1109/PARBSE.1990.77141

S. Pramanik, C. Severance, T. Rosenau

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引用次数: 1

Abstract

The design, implementation, and performance of a main memory file system are presented. The implementation is based on a two-stage abstract parallel processing model. The objective of this model is to maximize throughput and minimize response time. To maximize throughput, lock structures, access structures, and shared variables are distributed among the shared memories. A novel approach based on hash-based parallel accesses is used. The effect of lock conflict is minimized by an optimistic locking protocol. Analytical models are developed for hot spot memory accesses, distributed data accesses, and space-versus-time tradeoffs for fast accesses to records. On the basis of the performance results of these models, a high-speed KDL-RAM (key accessed, dynamically reconfigurable, distributed locked random-access memory) file system has been implemented on the Butterfly PLUS Parallel Processor. Various performance results of this system are given. It is shown that the performance improvement of this system is considerably better than BBN's Butterfly RAMFile system on the Butterfly PLUS Parallel Processor.<>

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用于并行计算机的高速KDL-RAM文件系统

介绍了一个主存文件系统的设计、实现和性能。该实现基于两阶段抽象并行处理模型。该模型的目标是最大化吞吐量和最小化响应时间。为了最大化吞吐量，锁结构、访问结构和共享变量分布在共享内存中。采用了一种新的基于哈希的并行访问方法。乐观锁定协议将锁冲突的影响降到最低。分析模型是为热点内存访问、分布式数据访问和快速访问记录的空间与时间权衡而开发的。基于这些模型的性能结果，在Butterfly PLUS并行处理器上实现了高速KDL-RAM(键访问、动态可重构、分布式锁定随机存取存储器)文件系统。给出了该系统的各项性能结果。结果表明，该系统在Butterfly PLUS并行处理器上的性能提升明显优于BBN的Butterfly RAMFile系统。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications

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