A parallel scheme for implementing multialphabet arithmetic coding in high-speed programmable hardware

S. Mahapatra, Kuldeep Singh
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引用次数: 5

Abstract

In this paper, a scheme is proposed for parallel-pipelined implementation of the multialphabet arithmetic-coding algorithm used in lossless data compression. Using this scheme, it is possible to parallelize both the encoding and decoding operations used respectively in data compression and decompression. The compression performance of the proposed implementation for both order 0 and order 1 models have been evaluated and compared with existing sequential implementations in terms of compression ratios as well as the execution time using the Canterbury corpus benchmark set of files. The proposed scheme also facilitates hardware realisation of the respective modules and hence is suitable for integration into embedded microprocessor systems, an important area where lossless data compression is applied.
一种在高速可编程硬件上实现多字母算术编码的并行方案
本文提出了一种用于无损数据压缩的多字母算术编码算法的并行流水线实现方案。使用这种方案,可以并行化分别用于数据压缩和解压缩的编码和解码操作。已经使用Canterbury语料库基准文件集,就压缩比和执行时间方面,评估了所提出的0阶和1阶模型实现的压缩性能,并与现有的顺序实现进行了比较。所提出的方案还促进了相应模块的硬件实现,因此适合集成到嵌入式微处理器系统中,这是应用无损数据压缩的重要领域。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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