{"title":"A merging network scheme that builds large sorting networks","authors":"K. Law, A. Leon-Garcia","doi":"10.1109/GLOCOM.1994.513317","DOIUrl":null,"url":null,"abstract":"We present a new scheme for building large sorting networks. The scheme is recursive in the sense of indicating how to build a large sorting network from modules of smaller sorting and merging networks. The scheme involves a regular wiring pattern between modules. When the scheme is applied to 2/spl times/2 comparison elements, we obtain a new sorting network with a wiring pattern that has fewer cross-over points than Batcher's (1968) networks. When the scheme is applied to modules of a given size, for example 32/spl times/32 single-chip sorters, then we obtain a multi-chip implementation of larger sorting networks. Thus the scheme presented allows us to circumvent technology limitations that currently limit the size of sorters that are implementable.","PeriodicalId":323626,"journal":{"name":"1994 IEEE GLOBECOM. Communications: The Global Bridge","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1994 IEEE GLOBECOM. Communications: The Global Bridge","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLOCOM.1994.513317","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We present a new scheme for building large sorting networks. The scheme is recursive in the sense of indicating how to build a large sorting network from modules of smaller sorting and merging networks. The scheme involves a regular wiring pattern between modules. When the scheme is applied to 2/spl times/2 comparison elements, we obtain a new sorting network with a wiring pattern that has fewer cross-over points than Batcher's (1968) networks. When the scheme is applied to modules of a given size, for example 32/spl times/32 single-chip sorters, then we obtain a multi-chip implementation of larger sorting networks. Thus the scheme presented allows us to circumvent technology limitations that currently limit the size of sorters that are implementable.