A partition level floorplan method based on data flow analysis for physical design of digital IC

Abstract

This paper presents a partition level floorplan method for physical design of digital integrated circuit, which based on data flow analysis. It uses Cadence company P&R tool innovus to make floorplan, and takes a X86 CPU's south bridge design for example to introduce how to use this method to guide floorplan in detail. This method is more effective to improve the quality of floorplan for advanced process technology and high speed IC design.