Heterogeneous Functional Units for High Speed Fault-Tolerant Execution Stage

Abstract

In modern processors it is difficult to implement a high speed and area effective fault-tolerant execution stage that can tolerate defects and hard faults. The structure of Functional Units (FU) is complicated, unlike registers or cache memory. Conventional approaches are able to tolerate faults but overhead is large. We propose Heterogeneous Functional Units (HFUs), with high speed and area effective fault-tolerant execution stages by using a combination of fast FUs and fault-tolerant FUs. Simulation results from SPEC2000 benchmarks show that HFUs have 99%(HFU-Det), 94.2%(HFU-1) of relative IPC for a simple duplication of fast FUs. HFU is faster than the simple duplication of fault-tolerant FUs, that have 84.0%.