Advanced Down-Counting Operation in SPICE

I. Guran, A. Florescu, L. Perisoara, M. Teodorescu, I. Bacîș, Alexandru Vasile
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Abstract

One of the most important steps in the circuit design is simulation, which is used to validate the circuit before the physical implementation. Simulation Program for Integrated Circuits Emphasis (SPICE) is a popular and accurate simulator where behavioral models of the circuits are needed in order to perform the simulation. Over the last decade, the digital and mixed-signal circuits have become the most encountered type of circuits, where the up and down counting operations are essential. There is a lot of research on up and down counters in the literature, but only the up-counting operation has been approached in SPICE until now. For this reason, in this article, an advanced down-counting operation modeling technique is proposed, which aims to model an any-number of bits down-counter accurately, focusing on eliminating the limitation given by the number of bits of a down-counter and providing a fast simulation time. The verification of the down-counter model is done using the SPICE-based simulator environment OrCAD Capture.
SPICE中的高级计数操作
电路设计中最重要的步骤之一是仿真,它用于在物理实现之前验证电路。集成电路重点仿真程序(SPICE)是一种流行的精确模拟器,其中需要电路的行为模型来进行仿真。在过去的十年中,数字和混合信号电路已经成为最常见的电路类型,其中上下计数操作是必不可少的。文献中对上下计数器的研究很多,但迄今为止在SPICE中只探讨了向上计数操作。为此,本文提出了一种先进的降计数运算建模技术,该技术旨在对任意位数的降计数器进行精确建模,重点是消除降计数器位数的限制,并提供快速的仿真时间。下计数器模型的验证是使用基于spice的仿真环境OrCAD Capture完成的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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