Embedded RAM testing

Abstract

Embedded RAMs are RAMs whose address, data and read/write controls can not be directly controlled or observed through the chip's I/O pins. Testing these memories, which are incorporated on a large percentage of VLSI devices, is naturally harder because of the lack of controllability of its inputs and observability of its outputs. Testing such RAMs is the theme of this paper. It brings to light the challenges involved in testing embedded RAMs, and discusses techniques such as design for testability (DFT) and built-in self test (BIST), which help in improving the testability of these RAMs.