Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs

Abstract

As process technology shrinks into the nanometer-scale, the CMOS-based Field Programmable Gate Arrays (FPGAs) face big challenges in the scalability of performance and power consumption. Multi-walled Carbon Nanotube (MWCNT) serves as a promising candidate for Cu interconnects due to superior conductivity. Moreover, Carbon Nanotube Field Transistor (CNFET) also emerges as a prospective alternative to the conventional CMOS device because of its higher power efficiency and larger noise margin. However, the MWCNT interconnects exhibit significant variations due to an immature fabrication process, leading to delay faults. Furthermore, the non-ideal CNFET fabrication process may generate a few metallic-CNTs (m-CNTs), rendering correlated faulty blocks. In this paper, we propose a ring oscillator (RO) based testing technique to detect delay faults due to the process variations of MWCNT interconnects. In addition, a novel circuit design based on the lookup table (LUT) is applied to speed up the fault testing of CNT-based FPGAs. Finally, we propose a testing algorithm to detect m-CNTs in configurable logic blocks (CLBs). Experimental results show that the test application time for a 6-input LUT can be reduced by 35.49% compared to the conventional testing method, and the proposed algorithm can also achieve a high fault coverage with lower testing overheads.