A Predictable Transactional Memory Architecture with Selective Conflict Resolution for Mixed-Criticality Support in MPSoCs

Abstract

Transactional memories can radically simplify the programming of mixed-criticality systems by offering atomicity, consistency and isolation guarantees between subsystems of different criticality. A major objective in mixed-criticality systems is a modular safety case where each subsystem is certified to the respective safety assurance level. The prerequisite for this modular certification is the prevention of any effect of low criticality subsystems on the temporal behavior of subsystems of higher criticality. This paper introduces a transactional memory architecture based on a time-triggered network-on-a-chip with fault isolation based on a TDMA scheme. The memory architecture contains a memory gateway for selective conflict resolution when committing transactions. The memory gateway triggers a rollback of a transaction in case higher criticality subsystems would be affected. The proposed transactional memory architecture ensures that the validation and certification of high criticality subsystems does not depend on subsystems with lower criticality.