FPGA-Driven Table System to Accelerate Network Flows

Abstract

Commercial products using hardware and firmware for high-speed network flow tracking are commonplace but typically restrict users to a few predefined options. Conversely, ensemble architectures with multiple network processing units (NPUs) and specialized accelerators are flexible enough for many tasks but relatively slow at routine flow management tasks. The paper presents a system that combines a field programmable gate array (FPGA)-driven table system with an ensemble network architecture. The system is especially effective when the FPGA system tracks flows and sends only selected packets to NPUs for further processing. The principal design goal is to achieve FPGA-level speed when processing tables for flows, actions, packet modification, key search and hash extraction and yet to allow users to initialize and dynamically modify the tables in terms of flexible, high-level packetC language types and structures.