Delay macromodels for the timing analysis of GaAs DCFL

Abstract

A timing macromodel for gallium arsenide direct-coupled FET logic (GaAs DCFL) cells is derived. It calculates the delay of a cell as a function of such parameters as transistor sizes, capacitive loading, fanout, and input switching time. Calculations based on the derived macromodel show excellent agreement with circuit simulation at two to three orders of magnitude savings in computation time.<>