Design and analysis of reversible multiplexer and demultiplexer using R-Gates

Abstract

The paper presents a reversible implementation of multiplexer and de-multiplexer, and evaluation of their quantum cost, gate count, garbage outputs and depth of the circuit. The simulation results are obtain edinXilinxISE version 14.1. Reversible logic circuits are designed and implemented using Verilog code. The circuit is beneficial for further designing of reversible digital designs with low power loss. The devices designed through this circuit are expected to have a better performance as compared to the existing circuits.