Yoav Katz, M. Rimon, A. Ziv
{"title":"A Novel Approach for Implementing Microarchitectural Verification Plans in Processor Designs","authors":"Yoav Katz, M. Rimon, A. Ziv","doi":"10.1007/978-3-642-39611-3_17","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":325700,"journal":{"name":"Haifa Verification Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Haifa Verification Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-3-642-39611-3_17","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2