Micro-operation perturbations in chip level fault modeling

Abstract

A determination is made of the best micro-operation perturbation for modeling faults at the chip level. The measure used is the gate level stuck-at-fault coverage achieved by the tests derived to cover the micro-operation perturbation faults. For small combination circuits, it is shown that perturbing the elements into the logic dual is a good choice. For large combinational circuits, it is shown that there is very little variation in the gate level coverage achieved by the various microoperation faults. In this case, if coverage is to be improved, the micro-operation perturbation method must be augmented by other techniques.<>