Methodology for Decoupled Simulation of SystemVerilog HDL Designs

Abstract

Agile hardware modeling using Hardware Description Languages (HDLs) such as SystemVerilog is greatly limited by the ability of those languages to model complex system abstractions. Often hardware designs rely on complex components not necessarily related with the task performed by the end product, for example components accomplishing debugging or instrumentation tasks. Leveraging hardware instrumentation through high-level programming languages helps designers to focus their attention on the hardware design. This allows to integrate models at different levels of abstraction more easily, enabling existing models written using high-level programming to be used in conjunction with low-level hardware components. In this article, we propose a methodology to enable interaction between components within hardware design projects and also external components written in high-level programming languages.