Enhancing the SRAM performance of gate-stacked DG-MOSFET

Abstract

Replacing the gate dielectric with a physically thicker layer of High-K material is a preferred choice at the Nano-scale level to alleviate the over increasing gate tunneling leakage. However directly depositing of High-K gate dielectric on silicon wafer would degrade the short channel performance. This can be improved by taking the gate stack engineering (High-K dielectric over SiO2). This paper investigates the SRAM performance of gate stack engineered double gate (DG) MOSFET for different interfacial layer thickness. The SRAM simulation is carried out by using 2D Sentaurus TCAD simulator. It is observed that scaling down the interfacial layer thickness improves the overall SRAM performance of gate stacked engineered DG-MOSFET. Subsequently, to further improve the performance gate stack engineering (High-K over interfacial layer of SiO2) is a preferred choice.