Characterization and modeling of bonded hydrophobic interfaces for high-power BIMOS-devices

38th IAS Annual Meeting on Conference Record of the Industry Applications Conference, 2003. Pub Date : 2003-10-12 DOI:10.1109/IAS.2003.1257708

D. Detjen, T. Plum, S. Schroder, R. D. De Doncker

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引用次数: 4

Abstract

In this paper, a detailed investigation regarding the suitability of silicon-silicon wafer bonding to realize novel high-power thyristor-type devices is presented. The electrical characteristics of the bonding interface are examined both theoretically and experimentally. Moreover, a physical model of the grain boundary in silicon is illustrated and the current flow mechanisms at the potential barrier are explained for unipolar as well as bipolar carrier transport. For bipolar current transport, the relation between minority carrier excess at the bonding interface and the modification of the potential barrier is analytically derived. The different current components at the grain boundary due to thermal emission and carrier recombination are determined. Based on this calculation, a negligible impact of the grain boundary under bipolar current condition, which has been already observed in finite element simulations, is predicted. Finally, experimental results for bonded psn-diode structures are presented further supporting the rapidly decreasing potential barrier at the bonding interface in conductivity modulated devices.

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大功率bimos器件键合疏水界面的表征与建模

本文详细研究了硅-硅晶圆键合技术在实现新型大功率晶闸管器件中的适用性。从理论和实验两方面考察了键合界面的电特性。此外，还说明了硅中晶界的物理模型，并解释了单极和双极载流子输运势垒处的电流流动机制。对于双极电流输运，分析推导了键合界面少数载流子过剩与势垒修正之间的关系。确定了晶界处由于热发射和载流子复合而产生的不同电流分量。在此基础上，预测了在双极电流条件下晶界的影响可以忽略不计，这在有限元模拟中已经观察到。最后，给出了键合psn-二极管结构的实验结果，进一步支持了电导率调制器件中键合界面电位势垒的快速下降。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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38th IAS Annual Meeting on Conference Record of the Industry Applications Conference, 2003.

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