A novel and efficient design of golay encoder for ultra deep submicron technologies

Abstract

This paper lays out two different approaches for generation of binary golay code (23, 12). Namely, Linear feedback shift register (LFSR) based CRC and hardware architecture based on CRC. There are certain disadvantages associated with these two architectures. To overcome those disadvantages, a new architecture has been proposed for binary golay code (23, 12) generation. This paper also presents an efficient hardware architecture to generate extended golay code (24, 12). High speed, low latency, low area and low power architecture has been designed and verified.