Cone clustering principles for parallel logic simulation

Abstract

Parallelization following the replicated worker principle can significantly accelerate functional logic simulation of microprocessor structures. Successful application of this method strongly depends on circuit model partitioning. We have developed a hierarchical partitioning strategy with prepartitioning and main partitioning as core phases that appear as bottom-up cone clustering. Cones can be seen as special areas of combinational logic which have the ability to directly influence storing or output elements of a circuit model under consideration. We describe and compare three of our cone clustering techniques which are based on a formal model of parallel logic simulation. Experimental results are given with respect to IBM processor structures ranging in their size from several hundred thousand to several million basic elements at a mixture of register-transfer- and gate level.