Massively parallel array processor for logic, fault, and design error simulation

Y. Hur, S. Szygenda, E. S. Fehr, G. Ott, Sungho Kang
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引用次数: 2

Abstract

Digital logic, fault, and error simulation of large VLSI circuits is one of the most compute-intensive tasks in digital systems analysis. This paper describes a massively parallel special purpose array processor, or hardware accelerator, for digital logic, fault, and error simulation. Hardware simulation is a viable approach for simulation of large systems, since simulation time increases rapidly as a function of the size and complexity of the systems to be simulated. In order to reduce the cost and to achieve high performance, a massively parallel array processor and new algorithms have been introduced. By executing an efficient and direct model of the design on the PE array, the architecture can provide high performance, similar to prototyping. Simulation results show that the hardware accelerator is orders of magnitude faster than software simulation.<>
用于逻辑、故障和设计错误仿真的大规模并行阵列处理器
大型VLSI电路的数字逻辑、故障和误差仿真是数字系统分析中计算最密集的任务之一。本文介绍了一种大规模并行专用阵列处理器,或称硬件加速器,用于数字逻辑、故障和错误仿真。硬件仿真是大型系统仿真的一种可行方法,因为仿真时间随着待仿真系统的大小和复杂性而迅速增加。为了降低成本和实现高性能,大规模并行阵列处理器和新的算法被引入。通过在PE阵列上执行高效和直接的设计模型,该架构可以提供类似于原型设计的高性能。仿真结果表明,硬件加速器的速度比软件仿真快几个数量级。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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