Enhanced concurrent error correcting arithmetic unit design using alternating logic

Abstract

Presents an enhanced concurrent error correcting arithmetic unit design methodology using alternating logic, which is motivated by the time shared triple modular redundancy (TMR) technique. With help from alternating logic, this new design approach will result in a higher reliability, i.e., 100% stuck-at faults can be detected, modest hardware delay and overhead. The basic idea is to add inverters and multiplexers in front of and behind the arithmetic unit and to let some control logic choose the path for the data. This design methodology can be applied to any system with hardware redundancy. For demonstration and comparison, 16-bit VLSI ripple carry adders are designed and verified using both the time shared TMR technique and the time shared TMR with alternating logic strategy. It is shown from the simulation results that the proposed approach has higher reliability with only a small increase in hardware delay.