{"title":"A video codec chipset for wireless multimedia networking","authors":"S. Molloy, R. Jain, K. Nishibori","doi":"10.1109/VLSISP.1995.527509","DOIUrl":null,"url":null,"abstract":"This paper describes a three-chip encoder/decoder for two-way video communications in a low-bit rate wireless environment. The chipset performs 2D and 3D wavelet transforms, scalar quantization, run-length/Huffman coding and bitstream formatting/parsing with fewer than 250 K total transistors. The codec provides high-quality video at bitrates between several megabits per second down to tens of kilobits per second, with a power consumption an order of magnitude lower than existing codecs. Robust decoding of corrupted bitstreams is enabled with a hierarchy of synchronization codewords and error concealment. The three chips include a programmable wavelet transform processor, a subband decoding processor and a subband encoding processor, occupying 36 mm/sup 2/, 42 mm/sup 2/ and 47 mm/sup 2/, respectively, in 1.2-micron CMOS.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Signal Processing, VIII","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSISP.1995.527509","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper describes a three-chip encoder/decoder for two-way video communications in a low-bit rate wireless environment. The chipset performs 2D and 3D wavelet transforms, scalar quantization, run-length/Huffman coding and bitstream formatting/parsing with fewer than 250 K total transistors. The codec provides high-quality video at bitrates between several megabits per second down to tens of kilobits per second, with a power consumption an order of magnitude lower than existing codecs. Robust decoding of corrupted bitstreams is enabled with a hierarchy of synchronization codewords and error concealment. The three chips include a programmable wavelet transform processor, a subband decoding processor and a subband encoding processor, occupying 36 mm/sup 2/, 42 mm/sup 2/ and 47 mm/sup 2/, respectively, in 1.2-micron CMOS.