Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOS

Abstract

Inter symbol interference introduced by fiber non-idealities such as polarization mode dispersion and chromatic dispersion would be one of the major limiting factors in achieving higher data rates in the existing Gigabit fiber-optic links. Receivers based on high speed ADCs followed by DSPs will be limited by the need for massive parallelization and interconnects. We propose analog signal processing based coherent optical link receiver to drastically reduce its power consumption, size and cost. A 40\, Gbps analog processing adaptive DP-QPSK (dual polarization quadrature phase shift keying) equalizer in 90\, nm CMOS technology is demonstrated using simulations, which dissipates 450\, mW of power. A complete analog processing receiver is expected to consume less than one-tenth of the power consumed by chip using ADCs followed by signal processing in DSP.