16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving −58dBFS noise and 4GHz bandwidth in 28nm CMOS

Abstract

This paper describes an 8GS/s 16-way time-interleaved ADC for a test and measurement application. Each ADC slice is a 1b/cycle, synchronous SAR operating at 500MS/s. The ADC slice schematic is shown in Fig. 16.5.1. The input is sampled using a thick-oxide NFET driven by a 1.9V buffer. After each conversion the hold node is reset differentially using a core NFET driven by a 1.1V buffer. The 10b DAC consists of two identical 5b halves separated by a bridging capacitor, Cbridge. Cbridge is sized to provide approximately 0.8b of redundancy between the MSB and LSB halves, enabling capacitor mismatch in the MSB half to be corrected digitally. The DAC is controlled by decision latches and uses the split-capacitor switching scheme [1] to provide a constant common mode to the comparator during conversion. The DAC comprises approximately 60% of the 250fF/side hold capacitance, resulting in a 1.2Vppd full-scale range when a 1V reference is used.