Fault tolerant circuits and probabilistically checkable proofs

A. Gál, M. Szegedy
{"title":"Fault tolerant circuits and probabilistically checkable proofs","authors":"A. Gál, M. Szegedy","doi":"10.1109/SCT.1995.514728","DOIUrl":null,"url":null,"abstract":"We introduce a new model of fault tolerance for Boolean circuits. We consider synchronized circuits and we allow an adversary to choose a small constant fraction of the gates at each level of the circuit to be faulty. We require that even in the presence of such faults the circuit compute a \"loose version\" of the given function. We show that every symmetric function has a small (size O(n), depth O(log n)) fault tolerant circuit in this model. We also show a perhaps unexpected relation between our model and probabilistically checkable proofs.","PeriodicalId":318382,"journal":{"name":"Proceedings of Structure in Complexity Theory. Tenth Annual IEEE Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Structure in Complexity Theory. Tenth Annual IEEE Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCT.1995.514728","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16

Abstract

We introduce a new model of fault tolerance for Boolean circuits. We consider synchronized circuits and we allow an adversary to choose a small constant fraction of the gates at each level of the circuit to be faulty. We require that even in the presence of such faults the circuit compute a "loose version" of the given function. We show that every symmetric function has a small (size O(n), depth O(log n)) fault tolerant circuit in this model. We also show a perhaps unexpected relation between our model and probabilistically checkable proofs.
容错电路和概率检验证明
提出了一种新的布尔电路容错模型。我们考虑同步电路,我们允许对手在电路的每一级选择一个小的恒定分数的门是错误的。我们要求,即使在存在这种故障的情况下,电路也要计算给定函数的“松散版本”。我们证明了在这个模型中,每个对称函数都有一个小的(大小为O(n),深度为O(log n))容错电路。我们还展示了我们的模型和概率可检验证明之间可能意想不到的关系。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信