Modeling and simulation of packaging substrate effects on radio frequency integrated circuits

Abstract

In this paper an analysis of the effects of integrated circuit packaging substrates on a radio frequency (RF) IC is presented. At RF frequencies the effects of packaging parasitics become crucial when assembling an RF system in package (SiP) or integrating a single die with a package. A differential buffer, which had been previously fabricated in a 90nm CMOS process is used as a vehicle to analyze the effects of packaging on performance. The integration of the buffer die with the package is modeled and analyzed.