A VPM (Virtual Pipelined Memory) architecture for a fast row-cycle DRAM

Abstract

We propose a Virtual Pipelined Memory (VPM) architecture for fast row-cycle by using a top-down design approach. A pipeline structure in the row path and integration of multiple SRAM buffers enable fast row-cycle. VPM shows higher performance than that of SDRAM by about 40% and that of VCM by about 20%. VPM maintains backward compatibility with a conventional SDRAM interface and consumes low power by adopting partial cell core activation.