Design and implementation of a flexible DMA controller in video codec system

Abstract

To meet rigorous high sustained bandwidth demand and exploit the data level access parallelism, a new architecture of DMA controller aiming at multimedia applications is proposed in this paper. Through analyzing the characteristics of video data transfer, we customize four shared channels with block address-conversion algorithm to adapt to many regular memory-access patterns. Furthermore, in order to transfer plenty of macro blocks whose addresses are not consecutive, channel descriptor model is applied into the design, which provides the most flexibility in managing the system's transfers. Besides, the design can also perform boundary extension, priority arbitrage and parameter prefetching as well as data rearrangement process. The proposed design is implemented in H.264/RVC encoder chip by SMIC 65nm technology with a clock frequency of 250MHz and 23.6K equivalent logic gates. Experimental results show that the customized design performs around 2~4 times faster than traditional DMA controller, and the lower ratio of setting time to transfer time proves that the burden of the processor is reduced significantly.