An Approach for Development of RISC- V Based Transport Layer Controller

Abstract

Most of the terminal nodes for information and telecommunication networks are developed using ASIC technology. Compared to FPGAs, it allows for lower power consumption and smaller area (size). However, in order for production to be profitable, chips must be produced in fairly large series - from several hundred copies. Because of this, terminal nodes must be universal enough to provide the ability to use them in networks for various purposes with different structures and architectures, different distributed computing schemes, with various rules of interaction between tasks, and with different memory architectures. Accordingly, networks may use different transport layer protocols. Additional actions in the interaction between the transport and application layers may be required in terminal nodes. Different schemes can be used to interact with memory, for example, Open MPI, MPICH, etc. To ensure performance in working with memory, it is very important that the corresponding scheme for interacting with memory is supported at the transport protocol level. Terminal nodes can be operated for several years. During this time period, new versions of transport protocols can be developed that are more suitable for the tasks being solved. It is very important that terminal nodes provide this new | universal functionality without replacing equipment. The transport controller unit must be dynamically reconfigurable to meet these requirements. Today, dynamically reconfigurable components are typically designed with using Field Programmable Gate Array (FPGA). However, the power consumption, area, timing characteristics (for example, the achievable clock frequency) of FPGA implementations are significantly worse than the same parameters of the implementations with using ASIC. These factors significantly limit the field of application of dynamically reconfigurable systems based on FPGAs. In previous works, we proposed an approach to the development of a dynamically reconfigurable transport protocol controller based on a dynamically reconfigurable automata and a dynamically reconfigurable DataPath. In this paper, we propose an approach to the development of a dynamically reconfigurable transport layer controller based on a processor core with RISC- V architecture. The paper presents several examples of using the proposed approach. We estimated the achievable parameters and overheads for these examples using a reconfigurable automata and reconfigurable DataPAth implementation and using a RISC-V based implementation.