A Continuous-Time Sigma-Delta Modulator with Compensating Transconductance Stages and RZ FIR-DAC

Abstract

This paper introduces an energy-efficient continuous-time sigma-delta modulator (CTSDM) that adopts transconductance stages compensating for the low frequency gain of the integrator, which injects an opposite signal into the input of the integrator to compensate for the degradation of performance and phase response caused by limited DC gain, and further reduces the requirement of each integrator to realize a low-power design. In addition, the association between return-to-zero (RZ) pulse and finite-impulse-response (FIR) digital-to-analog converter (DAC) in the feedback path of the modulator can reduce the influence of clock jitter and inter-symbol interference (ISI) on the signal-to-noise-and-distortion ratio (SNDR) and the linearity of the system. The implementation and experimental results show that the CTSDM achieves 98.7 dB SNDR in a 24 kHz bandwidth (BW), and dissipates 144.4$\mu$W under 1.2V power supply, this corresponds to a figure-of-merit (FoM) of 180.9 dB, this work is applied to codec applications in edge computing.