Configuration Mechanism of Software Defined Chip Applied in Signal Processing

Abstract

In order to give full play to the advantages of software defined chip hardware architecture, this paper designs a configuration mechanism of software defined chip applied in the field of signal processing. Firstly, this paper designs the configuration line execution iteration of PE (Processing Element); Secondly, the iteration times of PE top layer are designed; Thirdly design the number of PEA (Processing element array) top-level iterations; Finally, the implementation of matrix multiplication algorithm is used to analyze the hardware design results. Through simulation, the results show that, compared with TI c66x DSP, the clock cycle required to execute the same algorithm is reduced from 15325 to 200; The power consumption is reduced from 1092 mW to 420 mW, and the processing speed and power consumption are better than those of TI c66x DSP.