A 90nm 1-4.25-Gb/s Multi Data Rate Receiver for High Speed Serial Links

Abstract

This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity at 4.25-Gb/s by using offset corrected amplification, and performs clock-data-recovery with a digital algorithm that controls a recovered clock out of a phase interpolator. The receiver has been validated in 90 nm CMOS with 45 mW at 1.1 V supply voltage and demonstrated to achieve link over 30-meter AGW24 cable at 3.125 Gb/s with BER<10-5.