Leakage optimization of thick oxide IO/ESD transistors in 40nm global foundry process

Abstract

Thick Oxide IO/ESD transistor in 40nm Global Foundry process is studied for reducing leakage while being area efficient and maintaining performance. Gate induced drain leakage(GIDL) and source-drain leakage were found to be the major leakage contributors. Optimum architecture and sizing are found for IO/ESD design and presented in this paper.