A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM

Abstract

The density of DRAM has at last reached 256Mb at experimental level. Nevertheless, to realize a mass produced device, serious design problems still remain even if the performance related problems such as access time and power consumption are excluded. They are the problem of yield and test time explosion. This paper describes a new array architecture which implements a flexible redundant scheme and a new test time reduction capability with the reduction of chip size. In this architecture, the number of sense-amplifiers is reduced using a hierarchical bit-line (main/sub bit-line) without degradation of basic parameters such as bit-line parasitic capacitance and bit-line resistance. This redundant scheme features the flexibility of row replacement without a complicated control sequence. The new test mode is "block compare test" (BCT), in which the data stored in memory cells connected to two word-lines belonging to different blocks can be checked simultaneously for any data pattern.