{"title":"A fast architecture for deblocking filter in H.264/AVC using clock cycles saving process","authors":"M. Torabi, A. Vafaee, N. Movahhedinia","doi":"10.1109/MSPCT.2009.5426444","DOIUrl":null,"url":null,"abstract":"In this paper a fast architecture for Deblocking Filter in H.264/AVC video coding standard is presented. This architecture consists of a jump circuit which can increase the processing speed. To reduce the system complexity, we consider a single port external memory to be connected to our architecture. Accessing to the external memory is reduced by reusing stored blocks. Filtering operation is concurrent with reading/writing blocks. Simulation results show that the processing cycle count of the proposed architecture has decreased comparing to other similar architectures.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Multimedia, Signal Processing and Communication Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MSPCT.2009.5426444","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this paper a fast architecture for Deblocking Filter in H.264/AVC video coding standard is presented. This architecture consists of a jump circuit which can increase the processing speed. To reduce the system complexity, we consider a single port external memory to be connected to our architecture. Accessing to the external memory is reduced by reusing stored blocks. Filtering operation is concurrent with reading/writing blocks. Simulation results show that the processing cycle count of the proposed architecture has decreased comparing to other similar architectures.