Efficient Design of a Reversible Sorting Circuit

Abstract

Reversible logic is a very significant exposure for low-power consumption and faster computation in recent research areas. The aim of designing a reversible sorting circuit is to reduce power consumption and reliable communication. Two efficient sorting circuits are presented in this paper which can sort binary numbers in descending order. The proposed circuits includes 3 or 4 inputs where each input consists of 3 bits. Fredkin and Toffoli gates have been used to design the comparator. Fredkin gate has also been used for the proposed switch which generates result bit according to the comparator’s input. The proposed circuit needs 102 primary reversible gates for sorting 3 inputs and 170 gates for 4 inputs, 195 garbage outputs for 3 inputs and 325 garbage outputs for 4 inputs, 510 quantum cost for 3 inputs and 850 quantum cost for 4 inputs and (150α + 246β + 96γ) hardware complexity for 3 inputs and (250 + 410β + 160γ) hardware complexity for 4 inputs. In this modern era, sorting is used in many fields like pulse generation, counting and searching operations. Many research have been done regarding reversible sequential and combinational circuits but reversible sorting circuit is still an unexplored area, so this may be one of the pioneering works in this field.