High performance layout-friendly 64-bit priority encoder utilizing parallel priority look-ahead

Abstract

In this paper, a high-performance priority encoder is presented by using full custom approach. The proposed encoder provides both high- and low-priority functional with scalable design structure through a parallel look-ahead structure. A prefixing architecture is applied to minimize the critical path propagation delay and maximize the operating frequency. As a result, the proposed encoder is significant reduce the total critical delay by 53%, and the number of transistors by 7%, in addition it provides a regulated in building higher-order encoders. The results are conducted for different encoder inputs through TSMC 130nm CMOS technology.