Extended-forward architecture for simplified check node processing in NB-LDPC decoders

Cédric Marchand, E. Boutillon, Hassan Harb, L. Conde-Canencia, A. Ghouwayel
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引用次数: 2

Abstract

This paper focuses on low complexity architectures for check node processing in Non-Binary LDPC decoders. To be specific, we focus on Extended Min-Sum decoders and consider the state-of-the-art Forward-Backward and Syndrome-Based approaches. We recall the presorting technique that allows for significant complexity reduction at the Elementary Check Node level. The Extended-Forward architecture is then presented as an original new architecture for efficient syndrome calculation. These advances lead to a new architecture for check node processing with reduced area. As an example, we provide implementation results over GF(64) and code rate 5/6 showing complexity reduction by a factor of up to 2.6.
NB-LDPC解码器中简化检查节点处理的扩展前向架构
本文主要研究非二进制LDPC解码器中检查节点处理的低复杂度结构。具体来说,我们专注于扩展最小和解码器,并考虑最先进的前向后和基于综合征的方法。我们回顾一下在基本检查节点级别允许显著降低复杂性的预排序技术。然后提出了一种新颖的扩展前向体系结构,用于高效的综合征计算。这些进步导致了一种新的架构,用于减少面积的检查节点处理。作为一个例子,我们提供了在GF(64)和代码率5/6上的实现结果,显示复杂性降低了2.6倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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